|
Wednesday
August 22, 2007 |
Thursday
August 23, 2007 |
Friday
August 24, 2007 |
7:30 - 8:30 am |
Continental Breakfast
Registration Open
Check-in / Register on site |
Continental
Breakfast
Registration Open
Register for Tutorials |
Continental
Breakfast
Registration Open
Check-In for Tutorial Notes |
8:30 - 8:45 am |
Opening Remarks
John Lockwood , General Co-Chair
Fabrizio Petrini, General Co-Chair
Ron Brightwell, Program Co-Chair
Dhabaleswar(DK) Panda, Program Co-
Chair |
Opening Remarks
John Lockwood , General Co-Chair
Fabrizio Petrini, General Co-Chair
Ron Brightwell, Program Co-Chair
Dhabaleswar(DK) Panda, Program Co- Chair |
TUTORIALS
TUTORIAL 1
NetFPGA (Full Day)
Nick McKeown and John Lockwood, Glen Gibb, Jad Naous, Adam Covington, Stanford University
TUTORIAL 2
(Half Day)
Introduction to Programming High Performance Applications on the CELL Broadband Engine
Dr. Jakub Kurzak and Dr. Alfredo Buttari Innovative Computing Laboratory, University of Tennessee At Knoxville |
8:45 - 10:15 am |
SESSION 1
On Chip Networking
Session Chair: Dhabalaswar Panda (The Ohio State University) |
SESSION 4
Routing
Session Chair:
John Lockwood (Stanford University) |
Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects
Dongkook Park (Pennsylvania State University, USA); Reetuparna Das (Pennsylvania State University, USA); Chrysostomos Nicopoulos (PennsylvaniaState University, USA); Jongman Kim (Pennsylvania State University, USA); N. Vijaykrishnan (Pennsylvania State University, USA); Ravishankar Iyer (Intel Corp, USA); Chita Das (The Pennsylvania State University, USA) |
A Memory-Balanced Linear Pipeline Architecture for Trie-based IP Lookup on FPGAs
Weirong Jiang (University of Southern California, USA); Viktor Prasanna (University of Southern California, USA) |
Layout-Accurate Design and Implementation of a High-Throughput
Interconnection Network for Single-Chip Parallel Processing
Aydin Balkan (University of Maryland, USA); Michael Horak (University of Maryland, USA); Gang Qu (University of Maryland, USA);
Uzi Vishkin (University of Maryland, USA) |
Building a RCP (Rate Control Protocol) Test Network
Nandita Dukkipati (Stanford University, USA);
Glen Gibb (Stanford University, USA);
Nick McKeown (Stanford University, USA);
Jiang Zhu (Stanford University, USA) |
Photonic NoC for DMA Communications in Chip Multiprocessors
Assaf Shacham (Columbia University, USA); Benjamin G. Lee (Columbia University, USA); Alexsandr Biberman (Columbia University, USA); Keren Bergman (Columbia University, USA);
Luca P. Carloni (Columbia University, USA)
|
ElephantTrap: A low cost device for identifying large flows
Yi Lu (Stanford University, USA); Mei Wang (Stanford University, USA); Balaji Prabhakar (Stanford University, USA); Flavio Bonomi (Cisco Systems, USA) |
10:15 - 11 am |
Break |
11:00 - 12 pm |
Keynote:
Alex Dickinson, Luxtera
"CMOS Photonics - Bringing Moore's Law to Optical Interconnect" |
Keynote:
Dr. Tryggve Fossum, Intel
"On-Die Interconnect and Other Challenges for Chip-Level Multi-Processing" |
TUTORIALS (cont'd) |
Noon - 1:30 pm |
Lunch |
1:30
- 3:00 pm |
SESSION 2
Switch Architecture
Session Chair: Keren Bergman (Columbia University) |
SESSION 5
Performance Evaluation
Session Chair: Ron Brightwell (Sandia National Laboratories)
|
TUTORIALS (cont'd)
Tutorial 1 (cont'd)
NetFPGA
Nick McKeown and John Lockwood, Glen Gibb, Jad Naous, Adam Covington, Stanford University
Tutorial 3 (Half Day)
Design of Interconnection Networks
John Kim, Stanford University and Dennis Abts, Cray
|
Backlog Aware Low Complexity Schedulers for Input Queued Packet Switches
Aditya Dua (Stanford University, USA); Nicholas Bambos (Stanford University, USA); Wladek Olesinski (Sun Microsystems, USA); Hans Eberle (Sun Microsystems, USA); Nils Gura (Sun Microsystems Inc., USA) |
An Analysis of 10-Gigabit Ethernet Protocol Stacks in Multicore
Environments
Ganesh Narayanaswamy (Virginia Polytechnic Insititute and State University,USA); Pavan Balaji (Argonne National Laboratory, USA); Wu-chun Feng (Virginia Tech, USA |
Power Aware Management of Packet Switches
Lykomidis Mastroleon (Stanford Universiry, USA); Daniel O'Neill (Stanford University, USA);
Benjamin Yolken (Stanford University, USA); Nicholas Bambos (Stanford University, USA) |
Assessing the Ability of Computation/Communication Overlap and Communication Progress in Modern Interconnects
Mohammad Rashti (Queen's University, Canada); Ahmad Afsahi (Queen's University, Canada) |
Implementation of Dynamic Bandwidth Re-allocation in Optical Interconnects using Microring Resonators
Chander Kochar (University of Arizona, USA); Avinash Kodi (University of Arizona, USA);
Ahmed Louri (University of Arizona, USA) |
Performance Analysis and Evaluation of Mellanox ConnectX InfiniBand
Architecture with Multi-Core Platforms
Sayantan Sur (The Ohio State University, USA); Matthew Koop (The Ohio State University, USA); Lei Chai (The Ohio State University, USA); Dhabaleswar Panda (The Ohio State University, USA) |
3:00 - 3:30 pm |
BREAK |
3:30
- 4:30 pm |
SESSION 3
Support for Network Security
Session Chair: Fabrizio Petrini (IBM)
|
SESSION 6
OS/Network Interface Technology
Session Chair: Dennis Abts (Cray, Inc.) |
TUTORIALS (cont'd)
until 5 pm.
|
A Real-Time Worm Outbreak Detection System Using Shared Counters
Miad Faezipour (University of Texas at Dallas, USA); Mehrdad Nourani (University of Texas at Dallas, USA); Rina Panigrahy (Cisco Systems, USA) |
Memory Management Strategies for Data Serving with RDMA
Dennis Dalessandro (Ohio Supercomputer Center, USA); Pete Wyckoff (Ohio Supercomputer Center, USA) |
Prototyping Fast, Simple, Secure Switches for Ethane
Jianying Luo (Stanford University, USA); Justin Pettit (Stanford, USA); Martin Casado (Stanford University, USA); Nick McKeown (Stanford University, USA); John Lockwood (Washington University, USA)
|
Reducing the Impact of the Memory Wall for I/O Using Cache Injection
Edgar Leon (University of New Mexico, USA); Arthur Maccabe (University of New Mexico, USA); Kurt Ferreira (University of New Mexico, USA) |
4:30 - 5:30 pm |
Short Industry talks from Sponsors
Myricom: Myri-10G: 10-Gigabit Ethernet with optional special sauces Dr. Patrick Geoffray, Myricom
Synplicity: On-chip Debugging using Identify Pro Ashok Kulkarni, Synplicity
Quadrics: Elan5 Network Processor
Dr. Lee James Porter |
Closing Remarks
John Lockwood , General Co-Chair
Fabrizio Petrini, General Co-Chair
Ron Brightwell, Program Co-Chair
Dhabaleswar(DK) Panda, Program Co- Chair |
5:30 - 7:00 pm |
Reception & Dinner |
|
7:00 - 8:30 pm |
PANEL DISCUSSION
Multicore Interconnect: Scale-Up or Melt-down?
Moderator:
Dan Pitt, Director, Vquence Pty. Ltd.
Panelists:
Charlie Janac, President and CEO, Arteris
Arun Sharma, Performance Engineering, Google
Manu Thapar, Vice President, Platform Engineering, Yahoo
Drew Wingard, CTO, Sonics |