PLEASE NOTE:
Tutorials are on Wednesday

DEMOs in the Registration Lobby on
Thursday & Friday

[Go to REGISTER NOW!]
  Wednesday
August 17, 2005		 Thursday
August 18, 2005		 Friday
August 19, 2005
7:30 - 8:30 am Continental Breakfast
Registration Open
Check-in / Register for Tutorials 		Continental Breakfast
Registration Open
Check-in / Register on site		 Continental Breakfast
Registration Open
Check-in / Register on site
8:30 - 8:45 am TUTORIAL 1 FULL DAY
Using the Open Network Lab
Jon Turner  

TUTORIAL 2 AM only
Quality of Service in Global Grid Computing
Luca Valcarenghi 

TUTORIAL 4 FULL DAY
High-Speed networking: A Systematic Approach to High-Bandwith Low-Latency Communication
Dr. J. Sterbenz     		Opening Remarks
James Sterbenz, General Co-Chair
Dimitrios Stiliadis, General Co- Chair		 Opening Remarks
James Sterbenz, General Co-Chair
Dimitrios Stiliadis, General Co- Chair
8:45 - 9:45 am  Keynote: (abstract)
Network Infrastructure Security & Robustness: ongoing challenge for researchers and practitioners

Dr. Rav Yavatkar: Intel Fellow, Intel Corporate Technology Group Director, Systems Technology Lab, INTEL CORPORATION  

Keynote: (abstract)
Massively Parallel Systems: Headache or Sliced Bread?

Manish Gupta is a Research Staff Member and Senior Manager of the Emerging System Software department at the IBM T. J. Watson Research Center.
9:45 - 10:15 am Break Break + ongoing product demos in lobby
10:15 - Noon      (Tutorials 1, 2 & 4 continue)
 SESSION 1
Networks for Large-Scale Parallel Computers
Session Chair: TBD
SESSION 4
High Performance Routers
Session Chair: TBD

Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-scale Computer with Proximity Communication
Robert Drost, Craig Forrest, Bruce Guenin, Ron Ho, Ashok Krishnamoorty, Danny Cohen, John Cunningham, Bernanrd Tourancheau, Arthur Zingher, Alex Chow, Gary Lauterbach, Ivan Sutherland

 A Scalable Switch for Service Guarantees
Bill Lin, Isaac Keslassy
Optimised Global Reduction on QsNetII
 Duncan Roweth,, Ashley Pittman 		Design of Randomized Multichannel Packet Storage for High Performance Routers
Jonathan Turner, Patrick Crowley, Sailesh Kumar*
Control Path Implementation for a Low-Latency Optical HPC Switch
Cyriel Minkenberg, Francois Abel, Peter Mueller, Raj Krishnamurthy, Mitchell Gusat
Addressing Queuing Bottlenecks at High Speeds
Sailesh Kumar*, Patrick Crowley, Jonathan Turner
Breaking the Connection: RDMA Deconstructed
Rajeev Sivaram, Rama Govindaraju, Peter Hochschild, Robert Blackmore, Piyush Chaudhary
Noon - 1:30 pm Lunch Lunch + ongoing product demos in lobby
1:30 - 3:00 pm    TUTORIAL 3 (PM only)
Internet Infrastructure Security
Dr. G. Manimaran
 SESSION 2
Performance Evaluation of High-Performance Interconnects
Session Chair: TBD 		PANEL DISCUSSION (abstract)
EtherNET vs EtherNOT

Moderator: Fabrizio Petrini

Panelists:
Wu-chun Feng - Los Alamos National Laboratory (NET)
Srinidhi Varadarajan, Virginia Tech (NOT)
Moray McLaren, Quadrics (NOT)
Bart Stuck, CorEdge (NET)
Mike Kagan, Mellanox (NOT)

Can Memory-Less Network Adapters Benefit Next-Generation InfiniBand Systems?
Sayantan Sur, Abhinav Vishnu, Hyun-Wook Jin, Wei Huang and Dhabaleswar K. Panda
Initial Performance Evaluation of the Cray SeaStar Interconnect
Ron Brightwell, Keith Underwood
Performance Characterization of a 10-Gigabit Ethernet TOE
Wu-chun Feng, Pavan Balaji, Chris Baron. Laxmi Bhuyan, Dhabaleswar Panda
3:00 - 3:30 pm BREAK   BREAK + ongoing product demos in lobby
3:00 - 5:00 pm       (Tutorials 1, 3 & 4 continue)
 SESSION 3
Network Processors and Associative Technology
Session Chair: TBD 		SESSION 5
TCP and Switch Architecture
Session Chair: TBD
Hybrid Cache Architecture for High Speed Packet Processing
Zhen Liu, Kai Zheng and Bin Lin
 SIFT: Snort Intrusion Filter for TCP
Michael Attig, John Lockwood
High-Speed and Low-Power Network Search Engine Using Adaptive Block-Selection Scheme
Mohammad Akhbarizadeh*, Mehrdad Nourani, Rina Panigrahy, Samar Sharma		 Zero Copy Sockets Direct Protocol over InfiniBand - Preliminary Implementation and Performance Analysis
Dror Goldenberg, Michael Kagan, Ran Ravid, Michael Tsirkin
Design and Implementation of A Content-aware Switch using A Network Processor
Li Zhao, Yan Luo, Laxmi Bhuyan, Ravishankar Iyer
 Long Round-Trip Time Support with Shared-Memory Crosspoint Buffered Packet Switch
Ziqian Dong, Roberto Rojas-Cessa
Closing Remarks
Dimitrios Stiliadis, General Co- Chair
5:00 - 6:30 pm   Reception Dinner
with Poster Session (outside)

A Scalable, Self-Routed, Terabit Capacity, Photonic Interconnection Network Assaf Shacham, Benjamin Lee, Keren Bergman

Reconfigurable Networking Hardware: A Classroom Tool Martin Casado

Congestion Control in Lossless Networks: An In-depth Study of InfiniBand Mitchell Gusat, David Craddock, Wolfgang Denzel, Nan Ni, Gregory Pfister, William Rooney

Centralized and Distributed Grid Topology Discovery Service Implementations Luca Valcarenghi, Francesco Paolucci, Luca Foschini, Filippo Cugini, Piero Castoldi

PathScale InfiniPath -- A First Look Lloyd Dickman

  		 
6:30 - 8:00 pm PANEL DISCUSSION (abstract)
Impact of Grid Computing on Network Operators and HW Vendors

Moderator: Brian L. Tierney, Lawrence Berkeley National Laboratory

Panelists:
Bill St. Arnaud, CANARIE Inc.
Tal Lavian, Nortel Networks
Bill Johnston, Berkeley National Laboratory
Phil Papadopoulos, San Diego Supercomputing Center
Masum Z. Hasan, Cisco Systems
Wes Kaplow, QWEST
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